1. Field of the Invention
An aspect of the present invention relates to a semiconductor device having a structure for applying a voltage to a word line connected to a memory cell.
2. Description of the Related Art
In a semiconductor memory device, bit lines and word lines are arranged to extend to intersect each other, and a memory cell is provided in each intersectional region in which an associated one of the bit lines and that of the word lines intersect each other. The word lines extend across a memory cell area including a memory cell array along a given direction, and a voltage is applied to each memory cell through the word lines (see, e.g., JP-2008-047904-A). In JP-2008-047904-A, leakage current between adjacent word lines is suppressed by appropriately forming an end portion of each word line. However, with the recent micro-patterning of the memory cell and the reduction of the design rule thereof, there is a tendency that a word line width is decreased. In addition, according to the specifications of products, it is necessary to lengthen a word line length still more. In this case, the propagation delay of a signal easily occurs, thereby decreasing the speed of writing data to a memory cell.